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ltc2389-16 1 238916f typical application description 16-bit, 2.5msps sar adc with pin- configurable analog input range and 96db snr the lt c ? 2389-16 is a low noise, high speed 16- bit successive approximation register ( sar) adc. operating from a single 5 v supply, the ltc2389-16 supports pin- configurable fully differential (4.096 v), pseudo-differ- ential unipolar (0 v to 4.096 v), and pseudo-differential bipolar (2.048 v) analog input ranges, allowing it to interface with multiple signal chain formats without re- quiring additional level translation or signal conditioning. the ltc2389-16 achieves 1 lsb inl ( maximum), no missing codes at 16- bits, and 96.0db ( fully differential)/ 93.5db (pseudo differential) snr (typical). the ltc2389-16 includes a precision internal 4.096v reference, with a guaranteed 0.5% initial accuracy and a 20ppm/c ( maximum) temperature coefficient, as well as an internal reference buffer. fast 2.5 msps throughput with no cycle latency in the parallel interface modes makes the ltc2389-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considera- tions. the ltc2389-16 dissipates only 162.5mw at 2.5msps, while both nap and sleep power-down modes are provided to further reduce power consumption during inactive periods. features a pplications n 2.5msps throughput rate n 1lsb inl (max) n guaranteed 16-bit, no missing codes n pin-configurable analog input range: 4.096v fully differential 0v to 4.096v pseudo-differential unipolar 2.048v pseudo-differential bipolar n 96.0 db (fully differential)/ 93.5db (pseudo differential) snr ( typ ) at f in = 2khz n C116db (fully differential)/C112db (pseudo differential) thd ( typ ) at f in = 2khz n guaranteed operation to 125c n single 5v supply n internal 20ppm/c (max) reference n internal reference buffer n 162.5mw power dissipation at 2.5msps n no pipeline delay, no cycle latency n 1.8 v to 5v i/o voltages n parallel and serial i/o interface n 48-pin 7mm 7mm lqfp and qfn packages n medical imaging n high speed, wide dynamic range data acquisition n industrial process control n instrumentation n ate 32k point fft f smpl = 2.5msps, f in = 2khz sample clock 1f 10f 1.8v to 5v 5v 0.1f 10f 0.1f 10f a0 a1 mode0 mode1 reset pd cs ob/2c pd/fd busy cnvst parallel or serial interface 238916 ta01a in ? in + 1nf 10 10 49.9 49.9 gnd refsense refout refin ltc2389-16 16 bit vcm 1nf v dd ov dd + ? 4.096v 0v 0v 4.096v 0v 4.096v 0v 4.096v 0v 2.048v l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7705765. frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 ta01b snr = 96.0db thd = ?116db sinad = 96.0db sfdr = 117db
ltc2389-16 2 238916f supply voltage (v dd , ov dd ) ....................................... 6v ana log input voltage ( note 3) in + , in C , refin , cnvst ..... ( gn d C 0.3 v) to (v dd + 0.3 v) digital input voltage ( note 3) .......................... ( gn d C 0.3 v) to ( ov dd + 0.3 v) digital output voltage ( note 3) .......................... ( gn d C 0.3 v) to ( ov dd + 0.3 v) power dissipation .............................................. 50 0 mw (notes 1, 2) o r d er i n f ormation lead free finish tape and reel part marking* package description temperature range ltc2389cuk-16#pbf ltc2389cuk-16#trpbf ltc2389uk-16 48-lead 7mm 7mm plastic qfn 0c to 70c ltc2389iuk-16#pbf ltc2389iuk-16#trpbf ltc2389uk-16 48-lead 7mm 7mm plastic qfn C40c to 85c lead free finish tray part marking* package description temperature range ltc2389clx-16#pbf ltc2389clx-16#pbf ltc2389lx-16 48-lead 7mm 7mm plastic lqfp 0c to 70c ltc2389ilx-16#pbf ltc2389ilx-16#pbf ltc2389lx-16 48-lead 7mm 7mm plastic lqfp C40c to 85c ltc2389hlx-16#pbf ltc2389hlx-16#pbf ltc2389lx-16 48-lead 7mm 7mm plastic lqfp C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ a bsolute m aximum r atings 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd v dd v dd mode0 mode1 ob/2c a0 a1 d0 d1 d2 d3 13 14 15 16 17 18 19 20 21 22 23 24 d4 d5 d6 d7 gnd ov dd v dd gnd d8 d9/sdi d10/sdo d11/sck 48 47 46 45 44 43 42 41 40 39 38 37 gnd v dd v dd v dd gnd in + in ? gnd v dd refsense refin refout vcm gnd cnvst pd reset cs pd/fd busy d15 d14 d13 d12 top view lx package 48-lead (7mm 7mm) plastic lqfp t jmax = 150c, ja = 50c/w top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd v dd v dd mode0 mode1 ob/2c a0 a1 d0 d1 d2 d3 13 14 15 16 17 18 19 20 21 22 23 24 d4 d5 d6 d7 gnd ov dd v dd gnd d8 d9/sdi d10/sdo d11/sck 48 47 46 45 44 43 42 41 40 39 38 37 gnd v dd v dd v dd gnd in + in ? gnd v dd refsense refin refout vcm gnd cnvst pd reset cs pd/fd busy d15 d14 d13 d12 t jmax = 125c, ja = 29c/w exposed pad (pin 49) is gnd, must be soldered to pcb p in c on f iguration operating temperature range ltc 23 89 c ................................................ 0 c to 70 c ltc 23 89 i ............................................. C 40 c to 85 c ltc 23 89 h .......................................... C4 0 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) lx p ackage ....................................................... 30 0 c
ltc2389-16 3 238916f a nalog i nput the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in + absolute input range (in + ) (note 5) l C0.1 v ref + 0.1 v v in C absolute input range (in C ) fully differential (note 5) pseudo- differential unipolar ( note 5) pseudo-differential bipolar (note 5) l l l C0.1 C0.1 v ref /2 C 0.1 0 v ref /2 v ref + 0.1 0.1 v ref /2 + 0.1 v v v v in + C v in C input differential voltage range fully differential pseudo-differential unipolar pseudo-differential bipolar l l l Cv ref 0 Cv ref /2 v ref v ref v ref /2 v v v v cm input common mode voltage range fully differential l v ref /2 C 0.1 v ref /2 v ref /2 + 0.1 v i in analog input leakage current c- and i-grades h-grade l l C1 C2 1 2 a a c in analog input capacitance sample mode hold mode 45 5 pf pf cmrr input common mode rejection ratio 70 db v ihcnvst cnvst high level input voltage l 1.5 v v ilcnvst cnvst low level input voltage l 0.5 v i incnvst cnvst input current v in = 0v to v dd l C25 C60 a c onverter c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise fully differential pseudo-differential unipolar pseudo-differential bipolar 0.19 0.38 0.38 lsb rms lsb rms lsb rms inl integral linearity error fully differential (note 6) pseudo-differential unipolar (note 6) pseudo-differential bipolar (note 6) l l l C1 C1 C1 0.3 0.3 0.3 1 1 1 lsb lsb lsb dnl differential linearity error fully differential pseudo-differential unipolar pseudo-differential bipolar l l l C0.6 C0.7 C0.7 0.1 0.1 0.1 0.6 0.7 0.7 lsb lsb lsb zse zero-scale error fully differential (note 7) pseudo-differential unipolar (note 7) pseudo-differential bipolar (note 7) l l l C3 C4 C4 0 0 0 3 4 4 lsb lsb lsb zero-scale error drift 0.05 ppm/c fse full-scale error external reference (note 7) internal reference (note 7) l 0.15 0.15 % % full-scale error drift 5 ppm/c
ltc2389-16 4 238916f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v refout internal reference voltage refout tied to refin, i out = 0a 4.076 4.096 4.116 v v refout tempco i out = 0a (note 9) l 10 20 ppm/c refout output impedance C0.1ma i out 0.1ma 2.3 k refout line regulation v dd = 4.75v to 5.25v 0.3 mv/ v v ref converter refin voltage 4.076 4.096 4.116 v refin input impedance 74 k vcm output voltage i out = 0a 2.08 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs (notes 4, 8) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio fully differential, f in = 2khz pseudo-differential unipolar, f in = 2khz pseudo-differential bipolar, f in = 2khz l l l 94.4 91.2 91.7 96.0 93.2 93.5 db db db fully differential, f in = 2khz (h-grade) pseudo-differential unipolar, f in = 2khz (h-grade) pseudo-differential bipolar, f in = 2khz (h-grade) l l l 94.3 91.0 91.5 96.0 93.2 93.5 db db db snr signal-to-noise ratio fully differential, f in = 2khz pseudo-differential unipolar, f in = 2khz pseudo-differential bipolar, f in = 2khz l l l 95.1 91.7 92.1 96.0 93.2 93.5 db db db fully differential, f in = 2khz (h-grade) pseudo-differential unipolar, f in = 2khz (h-grade) pseudo-differential bipolar, f in = 2khz (h-grade) l l l 94.9 91.5 91.9 96.0 93.2 93.5 db db db thd total harmonic distortion fully differential, f in = 2khz, first 5 harmonics pseudo-differential unipolar, f in = 2khz, first 5 harmonics pseudo-differential bipolar, f in = 2khz, first 5 harmonics l l l C116 C112 C111 C103 C101 C102 db db db fully differential, f in = 2khz, first 5 harmonics (h-grade) pseudo-differential unipolar, f in = 2khz, first 5 harmonics (h-grade) pseudo-differential bipolar, f in = 2khz, first 5 harmonics (h-grade) l l l C116 C112 C111 C103 C101 C102 db db db sfdr spurious-free dynamic range fully differential, f in = 2khz pseudo-differential unipolar, f in = 2khz pseudo-differential bipolar, f in = 2khz l l l 104 102 102 117 113 112 db db db fully differential, f in = 2khz (h-grade) pseudo-differential unipolar, f in = 2khz (h-grade) pseudo-differential bipolar, f in = 2khz (h-grade) l l l 103 102 102 117 113 112 db db db C3db input bandwidth 50 mhz aperture delay 0.5 ns aperture jitter 1 ps rms transient response full-scale step 70 ns r e f erence c haracteristics dynamic a ccuracy
ltc2389-16 5 238916f digital i nputs a n d digital o utputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i out = C500a l ov dd C 0.2 v v ol low level output voltage i out = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma p ower r equirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units v dd supply voltage l 4.75 5 5.25 v ov dd supply voltage l 1.71 5.25 v i vdd core supply current 2.5msps sample rate 2.5msps sample rate, internal reference enabled l 32.5 34.1 36 ma ma i ovdd i/o supply current 2.5msps sample rate (c l = 15pf) 1.6 ma i pd power down current (i vdd + i ovdd ) conversion done, p d = ov dd , other digital inputs tied to ov dd or gnd l 15 250 a p d power dissipation 2.5msps sample rate conversion done, p d = ov dd , other digital inputs tied to ov dd or gnd 162.5 75 180 1250 mw w t iming c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) symbol parameter conditions min typ max units f smpl sampling frequency parallel output modes serial output mode l l 2.5 2.0 msps msps t conv conversion time l 245 280 310 ns t acq acquisition time t acq = t cyc C t conv C t busylh (note 10) l 77 110 ns t cyc time between cnvst l 400 ns t cnvstl cnvst low time l 20 ns t cnvsth cnvst high time l 200 ns t busylh cnvst to busy delay c l = 15pf l 13 ns t reseth reset pulse width l 200 ns t sck sck period (notes 5, 11) l 10 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns t dsck sck delay from cs l 10 ns t ssdi sdi setup time from sck l 2 ns
ltc2389-16 6 238916f figure 1. voltage levels for timing specifications note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground, or above v dd or ov dd , without latchup. note 4: v dd = 5v, ov dd = 5v, v ref = 4.096v external reference, f smpl = 2.5mhz, unless otherwise noted. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: fully differential zero-scale error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in twos complement format. unipolar zero-scale error is the offset voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. bipolar zero-scale error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. fully differential full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. unipolar full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. bipolar full-scale error is the worst-case deviation of the first and last code transitions from ideal and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 4.096v (fully differential), 0v to 4.096v (pseudo-differential unipolar), or 2.048v (pseudo-differential bipolar) input with a 4.096v reference voltage. note 9: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 10: guaranteed by design, not subject to test. note 11: a t sck period of 10ns minimum allows a shift clock frequency of up to 100mhz for rising capture. 0.8 ? ov dd 0.2 ? ov dd 50% 50% 238916 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay t hsdi sdi hold time from sck l 1 ns t dsdo sdo data valid delay from sck c l = 15pf l 9 ns t hsdo sdo data remains valid delay from sck c l = 15pf l 1 ns t ddbusyl data valid to busy c l = 15pf l 1 ns t en bus enable time after cs l 11 ns t dda1 data valid delay from a1 transition c l = 15pf l 8 ns t dis bus relinquish time after cs l 11 ns t iming c haracteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4)
ltc2389-16 7 238916f dc histogram (near full-scale) internal reference output vs temperature 32k point fft f smpl = 2.5msps, f in = 2khz snr, sinad vs input frequency integral nonlinearity vs output code differential nonlinearity vs output code dc histogram (zero-scale) thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, fully differential range (pd/fd = 0v), v cm = 2.048v, f smpl = 2.5msps, unless otherwise noted. output code inl error (lsb) 0 238916 g01 0.2 0.4 0.6 0.8 ?0.2 ?0.8 ?1.0 ?0.4 1.0 ?0.6 internal ref external ref 0 32768 16384 49152 65536 output code 0 dnl error (lsb) 0.1 0.2 0.3 0.4 0 ?0.1 32768 16384 49152 65536 ?0.4 ?0.5 ?0.2 0.5 ?0.3 238916 g02 internal ref external ref frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 g06 snr = 96.0db thd = ?116db sinad = 96.0db sfdr = 117db code ?2 0 1 counts 40000 0 80000 120000 160000 200000 280000 240000 ?1 2 238916 g03 code 32762 32764 32765 counts 40000 0 80000 120000 160000 200000 280000 240000 32763 32766 238916 g04 ?40 ?30 ?20 0 ?10 input level (db) snr, sinad (db) 96.0 97.0 95.5 95.0 96.5 238916 g09 snr sinad ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) reference output (v) 4.093 4.097 4.091 4.096 4.092 4.090 4.089 4.095 4.094 238916 g05 t c = 8ppm/c frequency (khz) 0 87 snr, sinad (db) 89 91 93 12.5 25 37.5 50 7562.5 87.5 95 97 88 90 92 94 96 100 238916 g07 sinad snr frequency (khz) 0 ?130 thd, harmonics (db) ?120 ?110 ?100 12.5 25 37.5 50 7562.5 87.5 ?90 ?85 ?125 ?115 ?105 ?95 100 238916 g08 thd 2nd 3rd
ltc2389-16 8 238916f supply current vs sampling frequency full-scale error vs temperature power-down current vs temperature cmrr vs input frequency offset error vs temperature supply current vs temperature t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, fully differential range (pd/fd = 0v), v cm = 2.048v, f smpl = 2.5msps, unless otherwise noted. thd, harmonics vs temperature, f in = 2khz snr, sinad vs temperature, f in = 2khz inl/dnl vs temperature ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) snr, sinad (db) 96 98 94 95 93 97 238916 g10 snr sinad ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) thd, harmonics (db) ?120 ?110 ?130 ?125 ?135 ?115 238916 g11 thd 2nd 3rd ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) inl/ dnl error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g12 max inl max dnl min dnl min inl ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) offset error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g13 ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) full-scale error (lsb) ?10 15 20 25 ?20 5 ?15 10 ?25 0 ?5 238916 g14 ? fs +fs ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) supply current (ma) 20 35 10 15 5 0 30 25 238916 g15 i vdd i ovdd ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) power-down current (a) 40 80 20 70 30 10 0 60 50 238916 g16 i vdd + i ovdd 1 100 1000 10 10000 sampling frequency (khz) 15 supply current (ma) 25 0 5 35 20 30 10 i ovdd i vdd 238916 g17 frequency (khz) 0 cmrr (db) 70 75 65 60 500 1000 250 750 1250 55 50 80 238916 g18
ltc2389-16 9 238916f integral nonlinearity vs output code differential nonlinearity vs output code dc histogram (near zero-scale) t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, pseudo-differential unipolar range (pd/fd = ov dd , ob/2c = ov dd ), f smpl = 2.5msps, unless otherwise noted. dc histogram (near full-scale) 32k point fft f smpl = 2.5msps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs temperature, f in = 2khz output code inl error (lsb) 0 238916 g19 0.2 0.4 0.6 0.8 ?0.2 ?0.8 ?1.0 ?0.4 1.0 ?0.6 internal ref external ref 0 32768 16384 49152 65536 output code dnl error (lsb) 238916 g20 0 0.1 0.2 0.3 0.4 0 ?0.1 32768 16384 49152 65536 ?0.4 ?0.5 ?0.2 0.5 ?0.3 internal ref external ref frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 g23 snr = 93.2db thd = ?112db sinad = 93.2db sfdr = 113db code counts 238916 g21 40000 0 80000 120000 160000 200000 240000 2 3 4 5 6 code counts 238916 g22 40000 0 80000 120000 160000 200000 240000 65530 65531 65532 65533 65534 ?40 ?30 ?20 0 ?10 input level (db) snr, sinad (db) 93.0 94.0 92.5 92.0 93.5 238916 g26 snr sinad ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) snr, sinad (db) 93 95 91 92 90 94 238916 g27 snr sinad 80 84 88 92 96 82 86 90 94 frequency (khz) 0 snr, sinad (db) 12.5 25 37.5 50 7562.5 87.5 100 238916 g24 sinad snr frequency (khz) 0 ?130 thd, harmonics (db) ?110 ?100 ?90 12.5 25 37.5 50 7562.5 87.5 ?80 ?75 ?120 ?125 ?115 ?105 ?95 ?85 100 238916 g25 thd 2nd 3rd
ltc2389-16 10 238916f t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, pseudo-differential unipolar range (pd/fd = ov dd , ob/2c = ov dd ), f smpl = 2.5msps, unless otherwise noted. thd, harmonics vs temperature, f in = 2khz inl/dnl vs temperature offset error vs temperature full-scale error vs temperature cmrr vs input frequency ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) thd, harmonics (db) ?115 ?105 ?130 ?120 ?125 ?135 ?110 238916 g28 thd 2nd 3rd ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) inl/ dnl error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g29 max inl max dnl min dnl min inl ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) offset error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g30 ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) full-scale error (lsb) 5 ?15 35 ?5 ?25 ?35 25 15 0 ?20 30 ?10 ?30 20 10 238916 g31 frequency (khz) 0 cmrr (db) 70 75 65 60 500 1000 250 750 1250 55 50 80 238916 g32
ltc2389-16 11 238916f t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, pseudo-differential bipolar range (pd/fd = ov dd , ob/2c = ov), f smpl = 2.5msps, unless otherwise noted. integral nonlinearity vs output code differential nonlinearity vs output code dc histogram (zero-scale) dc histogram (near full-scale) 32k point fft f smpl = 2.5msps, f in = 2khz snr, sinad vs input frequency thd, harmonics vs input frequency snr, sinad vs input level, f in = 2khz snr, sinad vs temperature, f in = 2khz output code inl error (lsb) 0 238916 g33 0.2 0.4 0.6 0.8 ?0.2 ?0.8 ?1.0 ?0.4 1.0 ?0.6 internal ref external ref 0 32768 16384 49152 65536 output code dnl error (lsb) 238916 g34 0 0.1 0.2 0.3 0.4 0 ?0.1 32768 16384 49152 65536 ?0.4 ?0.5 ?0.2 0.5 ?0.3 internal ref external ref frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 g37 snr = 93.5db thd = ?111db sinad = 93.5db sfdr = 112db code counts 238916 g35 40000 0 80000 120000 160000 200000 240000 ?2 ?1 0 1 2 code counts 238916 g36 40000 0 80000 120000 160000 200000 240000 32762 32763 32764 32765 32766 ?40 ?30 ?20 0 ?10 input level (db) snr, sinad (db) 93.5 94.5 93.0 92.5 94.0 238916 g40 snr sinad ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) snr, sinad (db) 93 95 91 92 90 94 238916 g41 snr sinad 80 84 88 92 96 82 86 90 94 frequency (khz) 0 snr, sinad (db) 12.5 25 37.5 50 7562.5 87.5 100 238916 g38 sinad snr frequency (khz) 0 ?130 thd, harmonics (db) ?110 ?100 ?90 12.5 25 37.5 50 7562.5 87.5 ?80 ?75 ?120 ?125 ?115 ?105 ?95 ?85 100 238916 g39 thd 2nd 3rd
ltc2389-16 12 238916f t ypical p er f ormance c haracteristics t a = 25c, v dd = 5v, ov dd = 2.5v, v ref = 4.096v external reference, pseudo-differential bipolar range (pd/fd = ov dd , ob/2c = ov), f smpl = 2.5msps, unless otherwise noted. thd, harmonics vs temperature, f in = 2khz inl/dnl vs temperature offset error vs temperature full-scale error vs temperature cmrr vs input frequency ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) thd, harmonics (db) ?115 ?105 ?130 ?120 ?125 ?135 ?110 238916 g42 thd 2nd 3rd ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) inl/ dnl error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g43 max inl max dnl min dnl min inl ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) offset error (lsb) 0 1.0 ?0.5 ?1.0 0.5 238916 g44 ?55 ?15 25 45 125 ?35 5 65 85 105 temperature (c) full-scale error (lsb) ?10 15 20 25 ?20 5 ?15 10 ?25 0 ?5 238916 g45 ? fs +fs frequency (khz) 0 cmrr (db) 70 75 65 60 500 1000 250 750 1250 55 50 80 238916 g46
ltc2389-16 13 238916f p in functions gnd (pins 1, 17, 20, 35, 41, 44, 48, exposed pad pin 49 ( qfn only)): ground. solder all gnd pins and exposed pad to the ground plane. v dd (pins 2, 3, 19, 40, 45, 46, 47): 5 v power supply. the range of v dd is 4.75 v to 5.25 v. bypass v dd network to gnd with a 0.1 f ceramic capacitor close to each pin and a 10f ceramic capacitor in parallel. mode0 (pin 4): data bus configuration input. this pin, in conjunction with pin 8 ( a1), controls the parsing and presentation of conversion results on the output data bus. based on the state of mode0, the bus is configured to provide either 16- bit/8-bit parallel (mode0 = 0), or serial (mode0 = 1) data, as described in table 1. digital outputs that are not active in a particular mode become hi-z. logic levels are determined by ov dd . for information regarding pin compatibility with 18-bit versions of the ltc2389 family, refer to the pin compatibility with ltc2389-18 section. mode1 (pin 5): data bus configuration input. this pin is reserved for use in 18- bit versions of the ltc2389 family, and for 16- bit versions of the family it should be driven to a logic low level. logic levels are determined by ov dd . for information regarding pin compatibility with 18-bit versions of the ltc2389 family, refer to the pin compatibility with ltc2389-18 section. ob/ 2c (pin 6): offset binary/ two s complement input. this pin, in conjunction with pin 30 ( pd/fd ), controls the analog input range of the converter and the binary format of the conversion result, as described in table 2. logic levels are determined by ov dd . a0 (pin 7): address bit 0 input. this pin is reserved for use in 18- bit versions of the ltc2389 family, and for 16- bit versions of the family it should be driven to a logic low level. logic levels are determined by ov dd . for information regarding pin compatibility with 18-bit versions of the ltc2389 family, refer to the pin compatibility with ltc2389-18 section. a1 (pin 8): address bit 1 input. this pin, in conjunction with pin 4 ( mode0), controls the parsing and presentation of conversion results on the parallel output data bus. when mode 0 = 0, the bus is configured to provide 16-bit/8-bit parallel data, and the logic input a1 determines which segment of the conversion result is driven on the upper and lower bytes of the bus, as described in table 1. when mode0 = 1, the output data bus is configured to provide serial data, and the logic input a1 has no effect on the parsing or presentation of the serial data. logic levels are determined by ov dd . for information regarding pin compatibility with 18- bit versions of the ltc2389 family, refer to the pin compatibility with ltc2389-18 section. d0 (pin 9): data bit 0. when mode0 = 0, this pin is bit 0 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d1 (pin 10): data bit 1. when mode0 = 0, this pin is bit 1 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d2 (pin 11): data bit 2. when mode0 = 0, this pin is bit 2 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d3 (pin 12): data bit 3. when mode0 = 0, this pin is bit 3 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d4 (pin 13): data bit 4. when mode0 = 0, this pin is bit 4 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d5 (pin 14): data bit 5. when mode0 = 0, this pin is bit 5 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d6 (pin 15): data bit 6. when mode0 = 0, this pin is bit 6 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d7 (pin 16): data bit 7. when mode0 = 0, this pin is bit 7 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . ov dd (pin 18): i/o interface power supply. the range of ov dd is 1.71 v to 5.25 v. bypass ov dd to gnd close to the pin with a 0.1 f and a 10 f ceramic capacitor in parallel. d8 (pin 21): data bit 8. when mode0 = 0, this pin is bit 8 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d9/sdi (pin 22): data bit 9/ serial data input. when mode0 = 0, this pin is bit 9 of the parallel data output bus, as described in table 1. when mode0 = 1, this pin
ltc2389-16 14 238916f is the serial data input, which can be used to daisy chain two or more converters on a single sdo line. the digital data level on sdi is output on sdo with a delay of 16 sck periods after the start of the read sequence. logic levels are determined by ov dd . d10/sdo (pin 23): data bit 10/ serial data output. when mode0 = 0, this pin is bit 10 of the parallel data output bus, as described in table 1. when mode0 = 1, this pin is the serial data output line, which serially outputs the result of the most recent conversion clocked by sck. the data is output msb first on the rising edge of sck. the data format is determined by the logic levels of pins pd/ fd and ob/ 2c , as described in table 2. logic levels are determined by ov dd . d11/sck (pin 24): data bit 11/ serial clock input. when mode0 = 0, this pin is bit 11 of the parallel data output bus, as described in table 1. when mode0 = 1, this pin this is the serial clock input. logic levels are determined by ov dd . d12 (pin 25): data bit 12. when mode0 = 0, this pin is bit 12 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d13 (pin 26): data bit 13. when mode0 = 0, this pin is bit 13 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d14 (pin 27): data bit 14. when mode0 = 0, this pin is bit 14 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . d15 (pin 28): data bit 15. when mode0 = 0, this pin is bit 15 of the parallel data output bus, as described in table 1. logic levels are determined by ov dd . busy (pin 29): busy output. this pin transitions low to high at the start of each conversion and stays high until the conversion is complete. the falling edge of busy can be used as the data-ready clock signal. logic levels are determined by ov dd . p in functions table 1. data bus configuration table. use input mode0 to select bus configuration based on application bus width. in the 16-bit /8-bit parallel configuration, input a1 controls mapping of upper and lower bytes of conversion result r[15:0] onto data bus pins d[15:0]. shaded cells denote bidirectional pins configured as inputs. bus configuration mode0 a1 d[15:12] d11 d10 d9 d8 d[7:0] 16-bit /8-bit parallel 0 0 r[15:8] r[7:0] 0 1 r[7:0] r[15:8] serial 1 x all hi-z sck sdo sdi all hi-z
ltc2389-16 15 238916f p in functions pd/ fd ( pin 30): pseudo- differential/ fully- differential input. this pin, in conjunction with pin 6 ( ob/2c ), controls the analog input range of the converter and the binary format of the conversion result, as described in table 2. logic levels are determined by ov dd . cs (pin 31): chip select input. the data i/o bus is enabled when cs is low and goes hi-z when cs is high. cs also gates the external shift clock. logic levels are determined by ov dd . reset ( pin 32): reset input. when this pin is brought high, the ltc2389-16 is reset. if this occurs during a conversion, the conversion is halted and the data bus becomes hi-z. logic levels are determined by ov dd . pd (pin 33): power-down input. when this pin is brought high, the ltc2389-16 is powered down and subse- quent conversion requests are ignored. before enabling power- down, the result of the last conversion result should be read. logic levels are determined by ov dd . cnvst (pin 34): conversion start input. a falling edge on this pin puts the internal sample-and-hold into the hold mode and starts a conversion. cnvst is independent of cs. logic levels are determined by v dd . vcm (pin 36): common mode analog output. typically the output voltage on this pin is 2.08 v. bypass to gnd with a 10f capacitor. refout (pin 37): internal reference output. connect this pin to refin if using the internal reference, giving a nominal reference voltage of 4.096 v. if an external reference is used, connect refout to ground to power down the internal reference. refin (pin 38): reference input. connect this pin to refout if using the internal reference, giving a nominal reference voltage of 4.096 v. an external reference can be applied to refin if a more accurate reference is required. if an external reference is used tie refout to ground to power down the internal reference. for increased filtering of reference noise, bypass this pin to refsense using a 1f, or larger, ceramic capacitor. refsense ( pin 39): reference input sense. do not connect refsense to ground when using the internal reference. if an external reference is used, connect refsense to the ground pin of the external reference. in C , in + (pin 42, pin 43): negative and positive analog inputs. the analog input range depends on the levels applied to pin 30 (pd/fd ) and pin 6 (ob/2c ), as described in table 2. table 2. analog input range and output binary format configuration table. use inputs pd/ fd and ob/2c to select converter analog input range and binary format of conversion result. pd/fd ob/2c analog input range binary format of conversion result 0 0 fully-differential two s complement 0 1 fully-differential offset binary 1 0 pseudo-differential bipolar two s complement 1 1 pseudo-differential unipolar straight binary
ltc2389-16 16 238916f f unctional b lock diagram 16-bit sampling adc parallel/ serial interface sdi sdo sck cs mode1 mode0 a1 a0 busy 238916 bd 16 bits 1x buffer refout refin in ? in + v dd ov dd ltc2389-16 vcm refsense control logic 4.096v reference cnvst pd/fd ob/2c reset pd gnd 16-bit or 8-bit bus
ltc2389-16 17 238916f d15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sdo sck previous conversion current conversion convert acquire cnvst busy d[15:0] 238916 td01 convert don?t care acquire cnvst busy cs = reset = 0 cs = reset = 0 t iming diagrams conversion timing using the parallel interface conversion timing using the serial interface
ltc2389-16 18 238916f a pplications i n f ormation overview the ltc2389-16 is a low noise, high speed 16- bit succes- sive approximation register ( sar) adc. operating from a single 5 v supply, the ltc2389-16 supports pin-con- figurable fully differential (4.096 v), pseudo-differential unipolar (0 v to 4.096 v) and pseudo-differential bipolar (2.048v) analog input ranges, allowing it to interface with multiple signal chain formats without requiring additional level translation or signal conditioning. the ltc2389-16 achieves 1 lsb inl ( maximum), no missing codes at 16-bits, and 96.0db ( fully differential)/93.5db (pseudo differential) snr (typical). the ltc2389-16 includes a precision internal 4.096v reference, with a guaranteed 0.5% initial accuracy and a 20ppm/c ( maximum) temperature coefficient, as well as an internal reference buffer. fast 2.5 msps throughput with no cycle latency in the parallel interface modes makes the ltc2389-16 ideally suited for a wide variety of high speed applications. an internal oscillator sets the conversion time, easing external timing considerations. the ltc2389-16 dissipates only 162.5 mw at 2.5 msps, while both nap and sleep power-down modes are provided to further reduce power consumption during inactive periods. converter operation the ltc2389-16 operates in two phases. during the ac- quisition phase, the charge redistribution capacitor d/a converter ( cdac) is connected to the in + and in C pins to sample the differential analog input voltage. a falling edge on the cnvst pin initiates a conversion. during the conversion phase, the 16- bit cdac is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the reference voltage ( e.g., v ref / 2, v ref / 4 v ref / 65536) using a differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16- bit digital output code for parallel or serial transfer. transfer function the ltc2389-16 digitizes the full-scale voltage of 2 ? v ref in fully-differential mode and v ref in pseudo-differential mode, into 2 16 levels. with v ref = 4.096 v, the resulting lsb sizes in fully- differential and pseudo- differential mode are 125 v and 62.5 v, respectively. the binary format of the conversion result depends on the logic levels on pins pd/fd and ob/2c , as described in table 2. the ideal twos complement transfer function is shown in figure 2, while the ideal straight binary transfer function is shown in figure 3. the ideal offset binary transfer function can be obtained from the twos complement transfer function by inverting the most significant bit (msb) of each output code. figure 2. ltc2389-16 tw o s complement transfer function. offset binary transfer function can be obtained by inverting the most significant bit (msb) of each output code figure 3. ltc2389-16 straight binary transfer function input voltage (v) 0v output code (two?s complement) ?1 lsb 238916 f02 011...111 011...110 000...001 000...000 100...000 100...001 111...110 1 lsb bipolar zero 111...111 fsr/2 ? 1lsb ?fsr/2 fsr = +fs ? ?fs 1lsb = fsr/65536 input voltage (v) output code (straight binary) 238916 f03 111...111 111...110 100...001 100...000 000...000 000...001 011...110 unipolar zero 011...111 fsr ? 1lsb 0v fsr = +fs 1lsb = fsr/65536
ltc2389-16 19 238916f a pplications i n f ormation analog input the analog inputs of the ltc2389-16 can be pin configured to accept one of three input voltage ranges: fully differential (4.096v ), pseudo - differential unipolar (0 v to 4.096v ), and pseudo-differential bipolar (2.048 v). in all three ranges, the adc samples and digitizes the voltage difference between the two analog input pins (in + C in C ), and any unwanted signal that is common to both inputs is reduced by the common mode rejection ratio ( cmrr) of the adc. independent of the selected range, the analog inputs can be modeled by the equivalent circuit shown in figure 4. the diodes at the input provide esd protection. in the acquisition phase, each input sees approximately 40pf (c in ) from the sampling cdac in series with 40 ( r in ) from the on-resistance of the sampling switch. the inputs draw a small current spike while charging the c in capacitors during acquisition. during conversion, the analog inputs draw only a small leakage current. pseudo-differential unipolar input range in the pseudo-differential unipolar input range, the adc digitizes the differential analog input voltage (in + C in C ) over a span of (0 v to v ref ). in this range, a single-ended unipolar input signal, driven on the in + pin, is measured with respect to the signal ground reference level, driven on the in C pin. the in + pin is allowed to swing from (gnd C 0.1 v) to (v ref + 0.1 v), while the in C pin is restricted to (gnd 0.1 v). unwanted signals common to both inputs are reduced by the cmrr of the adc. pseudo-differential bipolar input range in the pseudo-differential bipolar input range, the adc digitizes the differential analog input voltage (in + C in C ) over a span of (v ref /2). in this range, a single-ended bipolar input signal, driven on the in + pin, is measured with respect to the signal mid-scale reference level, driven on the in C pin. the in + pin is allowed to swing from (gnd C 0.1 v) to ( v ref + 0.1 v), while the in C pin is restricted to (v ref / 2 0.1 v). unwanted signals common to both inputs are reduced by the cmrr of the adc. input drive circuits a low impedance source can directly drive the high im- pedance inputs of the ltc2389-16 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis- tortion performance of the adc. minimizing settling time is important even for dc signals because the adc inputs draw a current spike when entering acquisition. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2389-16. the ampli- fier provides low output impedance enabling fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the current spike drawn by the adc inputs when entering acquisition. figure 4. equivalent circuit for the differential analog input of the ltc2389-16 in + r in 40 r in 40 c in 40pf c in 40pf v dd v dd bias voltage in ? 238916 f04 fully differential input range the fully differential input range provides the widest input signal swing, configuring the adc to digitize the differential analog input voltage (in + C in C ) over a span of (v ref ). in this range, the in + and in C pins should be driven 180 degrees out- of- phase with respect to each other, centered around a common mode voltage (in + + in C )/2 that is restricted to (v ref / 2 0.1 v). both the in + and in C pins are allowed to swing from (gnd C 0.1v) to (v ref + 0.1 v). unwanted signals common to both inputs are reduced by the cmrr of the adc.
ltc2389-16 20 238916f a pplications i n f ormation input filtering the noise and distortion of the buffer amplifier and other supporting circuitry must be considered since they add to the adc noise and distortion . a buffer amplifier with low noise density must be selected to minimize snr degradation. a filter network should be placed between the buffer output and adc input to both minimize the noise contribution of the buffer and reduce disturbances reflected into the buffer from adc sampling transients. a simple one-pole lowpass rc filter is sufficient for many applications. it is important that the rc time constants of this filter be small enough to allow the analog inputs to completely settle to 16- bit resolution within the adc acquisition time (t acq ), as insufficient settling can limit inl and thd performance. in many applications an rc time constant of 10 ns is fast enough to allow for sufficient transient settling during acquisition while simultaneously filtering driver wideband noise. often it is also beneficial to add small series resistors between the primary lowpass rc filter and the adc inputs. these resistors, in conjunction with the adc sampling capacitance c in and sampling switch resistance r in , form a second lowpass rc filter which further limits high- frequency driver noise as well as reduces the magnitude of the current spike drawn by the analog inputs when entering acquisition. the time constant of this secondary lowpass filter also directly affects settling of the analog inputs during acquisition and must be kept fast. in many applications 49.9 series resistors allow for sufficient transient settling during acquisition while providing useful additional filtering of wideband driver noise. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. fully differential inputs the ltc2389-16 accepts fully differential input signals directly. for most fully differential applications, it is recommended that the ltc2389-16 be driven using the lt6201 adc driver configured as two unity-gain buffers, as shown in figure 5 a. the lt6201 combines fast settling and good dc linearity with a 0.95nv/ hz input-referred noise density, enabling it to achieve the full adc data sheet snr and thd specifications, as shown in the fft plot in figure 5 b. this topology may also be used to buf- fer single-ended signals and achieves full adc data sheet snr and thd specifications in both pseudo-differential input modes, as shown in the fft plots in figures 5 c and 5d.
ltc2389-16 21 238916f a pplications i n f ormation figure 5a. lt6201 buffering a fully-differential or single-ended signal source figure 5 b . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 5 a; driven with fully differential inputs figure 5 c . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 5 a; driven with unipolar inputs figure 5 d . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 5 a; driven with bipolar inputs 238916 f05a in ? in + 1nf 10 10 1/2 lt6201 lowpass filters 1/2 lt6201 ltc2389-16 1nf + ? + ? 49.9 49.9 4.096v 0v 0v 4.096v 0v 4.096v 0v 4.096v 0v 2.048v frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f05b snr = 96.0db thd = ?116db sinad = 96.0db sfdr = 117db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f05c snr = 93.2db thd = ?112db sinad = 93.2db sfdr = 113db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f05d snr = 93.5db thd = ?111db sinad = 93.5db sfdr = 112db
ltc2389-16 22 238916f a pplications i n f ormation figure 6a. lt6231 buffering a fully-differential or single-ended signal source figure 6 b . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 6 a; driven with fully differential inputs figure 6 c . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 6 a; driven with unipolar inputs figure 6 d . 32 k point fft f smpl = 2.5msps, f in = 2 khz, for circuit shown in figure 6 a; driven with bipolar inputs 238916 f06a in ? in + 1nf 15 15 1/2 lt6231 lowpass filters 1/2 lt6231 ltc2389-16 1nf + ? + ? 49.9 49.9 4.096v 0v 0v 4.096v 0v 4.096v 0v 4.096v 0v 2.048v frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f06b snr = 95.7db thd = ?115db sinad = 95.6db sfdr = 116db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f06c snr = 92.4db thd = ?112db sinad = 92.3db sfdr = 113db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f06d snr = 92.7db thd = ?110db sinad = 92.6db sfdr = 111db in applications where slightly degraded snr and thd performance is acceptable, it is possible to drive the ltc2389-16 using the lower power lt6231 adc driver configured as two unity-gain buffers, as shown in figure?6 a. the rc time constant of the output lowpass filter is larger in this topology to limit the high frequency noise contribution of the lt6231. as shown in the fft plots in figures 6 b-6d, this circuit achieves 95.7 db snr and C115 db thd in fully differential input mode , 92.4db snr and C112 db thd in unipolar input mode, and 92.7db snr and C110db thd in bipolar input mode.
ltc2389-16 23 238916f a pplications i n f ormation figure 7a. lt6201 converting a 0v to 4.096v single-ended signal to a 4.096v fully-differential signal figure 7b. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 7a 238916 f07a in ? in + 1nf 10 10 lowpass filters ltc2389-16 330pf 1nf 4.096v 0v 4.096v 0v 4.096v 0v + ? + ? 402 402 1/2 lt6201 v cm = 2.048v 1/2 lt6201 + ? 330pf 49.9 49.9 frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f07b snr = 95.6db thd = ?112db sinad = 95.6db sfdr = 114db single-ended to differential conversion in some applications it may be desirable to convert a single- ended unipolar or bipolar signal to a fully- differential signal prior to driving the ltc2389-16 to take advantage of the higher snr of the ltc2389-16 in fully differential input mode. the lt6201 adc driver configured in the topology shown in figure 7 a can be used to convert a 0v to 4.096 v single-ended input signal to a fully-differential 4.096v output signal. the rc time constant of the output lowpass filters is chosen to allow for sufficient transient settling of the ltc2389-16 analog inputs dur - ing acquisition. this wide filter bandwidth, coupled with the relatively high wideband noise of the single- ended to differential conversion circuit, limits the achievable snr of this topology to 95.6 db, as shown in the fft plot in figure 7 b.
ltc2389-16 24 238916f a pplications i n f ormation an alternate single-ended to differential topology em- ploying the lt6231 followed by the lt6201 is shown in figure?8 a. this topology enables additional band-limiting of the wideband noise of the single-ended to differential conversion circuit using lowpass filters a without affect- ing the settling at the inputs of the ltc2389-16 during acquisition. this circuit achieves the full adc data sheet snr specifications, as shown in the fft plot in figure 8b. figure 8b. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 8a figure 8a. lt6231 converting a 0v to 4.096v single-ended signal to a 4.096v fully-differential signal followed by lt6201 buffering fully-differential signal 238916 f08a in ? in + 1nf 10 10 1/2 lt6201 lowpass filters b 1/2 lt6201 ltc2389-16 1nf + ? + ? 10nf 50 50 lowpass filters a 10nf + ? + ? 1k 1k 1/2 lt6231 1/2 lt6231 + ? 4.096v 0v 4.096v 0v 4.096v 0v v cm = 2.048v 49.9 49.9 frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f08b snr = 96.0db thd = ?116db sinad = 96.0db sfdr = 117db
ltc2389-16 25 238916f figure 9a. lt6200 buffering a single-ended signal source a pplications i n f ormation single-ended unipolar and bipolar inputs the ltc2389-16 accepts both single-ended unipolar and single-ended bipolar input signals directly. for most single-ended applications, it is recommended that the ltc2389-16 be driven using the lt6200 adc driver con- figured as a unity-gain buffer, as shown in figure 9 a. the lt6200 combines fast settling and good dc linearity with a 0.95nv/ hz input-referred noise density, enabling it to achieve the full adc data sheet snr and thd specifica- tions in both pseudo-differential input modes, as shown in the fft plots in figures 9b and 9c. figure 9c. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 9a; driven with bipolar inputs figure 9b. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 9a; driven with unipolar inputs 238916 f09a in ? in + 1nf 10 lowpass filter ltc2389-16 lt6200 + ? 4.096v 0v 0v 4.096v 0v 2.048v 49.9 49.9 frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f09b snr = 93.2db thd = ?112db sinad = 93.2db sfdr = 113db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f09c snr = 93.5db thd = ?111db sinad = 93.5db sfdr = 112db
ltc2389-16 26 238916f in applications where slightly degraded snr and thd performance is acceptable, it is possible to drive the ltc2389-16 using the lower power LT6230 adc driver configured as a unity-gain buffer, as shown in figure ?10 a. the rc time constant of the output lowpass filter is larger in this topology to limit the high frequency noise contribution of the LT6230. as shown in the fft plots in figures?10b and 10 c, this circuit achieves 92.5 db snr and C112 db thd in unipolar input mode and 92.8 db snr and C111db thd in bipolar input mode. note that in the circuits of figures 9 a and 10 a, the source impedance of the signal applied to in C directly affects input settling time during signal acquisition. in single-ended applications where the impedance of this reference signal is intrinsically high, the dual-buffer approach shown in figures 5 a and 6 a will provide for faster acquisition time and better distortion performance from the adc. figure 10b. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 10a; driven with unipolar inputs figure 10c. 32k point fft f smpl = 2.5msps, f in = 2khz, for circuit shown in figure 10a; driven with bipolar inputs a pplications i n f ormation 238916 f10a in ? in + 1nf 15 lowpass filter ltc2389-16 LT6230 + ? 49.9 49.9 4.096v 0v 0v 4.096v 0v 2.048v figure 10a. the LT6230 buffering a single-ended signal source frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f10b snr = 92.5db thd = ?112db sinad = 92.5db sfdr = 112db frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f10c snr = 92.8db thd = ?111db sinad = 92.7db sfdr = 112db
ltc2389-16 27 238916f adc reference a low noise, low temperature drift reference is critical to achieving the full data sheet performance of the adc. the ltc2389-16 provides an excellent internal refer- ence with a 20ppm/c ( maximum) temperature coef- ficient. if even better accuracy is required, an external reference can be used. in both cases, the high speed, low noise internal reference buffer is employed and cannot be bypassed. the buffer contributes a signal- dependent noise term to the converter with a typical standard deviation of: (v in + ? v in C ) v ref ? 16v rms , which accounts for the increase in transition noise between zero-scale and full-scale inputs. the reference voltage applied to refin adds a similar signal-dependent noise term, but its magnitude is limited by a 4khz (typical) lowpass filter in the internal buffer, making this term negligible in most cases. internal reference to use the internal reference, simply tie the refout and refin pins together. this connects the 4.096 v output of the internal reference to the input of the internal reference buffer. the output impedance of the internal reference is approximately 2.3 k and the input impedance of the internal reference buffer is about 74k . it is recommended refin be bypassed to refsense with a 1 f, or larger, capacitor to filter the output noise of the internal refer- ence. do not ground the refsense pin when using the internal reference. external reference an external reference can be used with the ltc2389 - 16 when even higher performance is required. the ltc665 5 offers 0.025% ( maximum) initial accuracy and 2ppm/c ( maximum) temperature coefficient for high precision applications. the ltc6655 is fully speci- fied over the h- grade temperature range and complements the extended temperature operation of the ltc2389-16 up to 125 c. when using an external reference, connect the reference output to the refin pin and connect the refout pin to ground. the refsense pin should be connected to the ground of the external reference. a pplications i n f ormation figure 11. 32k point fft of ltc2389-16, f smpl = 2.5msps, f in = 2khz dynamic performance fast fourier transform ( fft ) techniques are used to test the adc s frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and ana- lyzing the digital output using an fft algorithm, the adc s spectral content can be examined for frequencies outside the fundamental. the ltc2389-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band-limited to frequencies from above dc and below half the sampling frequency. figure 11 shows that the ltc2389-16 achieves a typical sinad of 96.0db ( fully differential) at a 2.5mhz sampling rate with a 2khz input. signal-to-noise ratio (snr) the signal-to-noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 11 shows that the ltc2389-16 achieves a typical snr of 96.0db ( fully differential) at a 2.5mhz sampling rate with a 2 khz input. frequency (khz) 0 amplitude (dbfs) ?60 ?40 ?20 ?80 ?100 500 250 750 1000 1250 ?160 ?180 ?120 0 ?140 238916 f11 snr = 96.0db thd = ?116db sinad = 96.0db sfdr = 117db
ltc2389-16 28 238916f total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ v n 2 v1 where v 1 is the rms amplitude of the fundamen- tal frequency and v2 through v n are the amplitudes of the second through nth harmonics, respectively . figure 11 shows that the ltc2389-16 achieves a typical thd of C116db ( fully differential) at a 2.5 mhz sampling rate with a 2khz input. power considerations the ltc2389-16 provides two sets of power supply pins: the 5 v core power supply (v dd ) and the digital input/ output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2389-16 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5v and 3.3 v systems. both the v dd and ov dd supply networks should be bypassed to gnd with a 0.1 f ceramic capacitor close to each pin and a 10 f ceramic capacitor in parallel. figure 12. nap mode timing for the ltc2389-16 power supply sequencing the ltc2389-16 does not have any specific power supply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2389 - 16 has an internal power-on reset ( por) circuit which resets the converter on initial power-up or whenever the power supply voltage drops below 2.5 v. once the supply volt- age re-enters the nominal supply voltage range, the por reinitializes the adc. with the por, the result of the first conversion is valid after power-up as long as the reference has been given sufficient time to settle. nap mode the ltc2389-16 can be put into nap mode after a conver- sion has been completed to reduce the power consumption between conversions. in this mode some of the circuitry on the device is turned off. nap mode is enabled by keeping cnvst low between conversions, as shown in figure 12. to initiate a new conversion after entering nap mode, bring cnvst high and hold for at least 200 ns before bringing it low again. a pplications i n f ormation cnvst busy nap t conv t acq nap mode 238916 f12 t cnvsth
ltc2389-16 29 238916f figure 13. supply current vs sampling frequency. power dissipation of the ltc2389-16 decreases with decreasing sampling frequency 1 100 1000 10 10000 sampling frequency (khz) 15 supply current (ma) 25 0 5 35 20 30 10 i ovdd i vdd 238916 f13 power shutdown mode when pd is tied high, the ltc2389-16 enters power shutdown. in this state, all internal functions, including the reference, are turned off and subsequent conversion requests are ignored. before entering power shutdown, the digital output data should be read. if a request for power shutdown occurs during a conversion, the conversion will finish and then the device will power down, but the data from that conversion should be read only after power shutdown mode has ended. in this mode, power consumption drops to a typical value of 75 w from 162.5 mw. this mode can be used if the ltc2389-16 is inactive for a long period of time and the user wants to minimize power dissipation. recovery from power shutdown mode to end the power shutdown and begin powering up the internal circuitry, return the pd pin to a low level. if the internal reference is used, the 2.3 k output impedance with the 1 f bypass capacitor on the refin/refout pins will be the main time constant for the power-on recovery time. if an external reference is used, typically allow 5ms for recovery before initiating a new conversion. power dissipation vs sampling frequency when nap mode is employed, the power dissipation of the ltc2389-16 will decrease as the sampling frequency is reduced, as shown in figure 13. this decrease in average power dissipation occurs because a portion of the circuitry on the ltc2389-16 is turned off during nap mode and the fraction of the conversion cycle (t cyc ) spent napping increases as the sampling frequency (f smpl ) is decreased. timing and control cnvst timing the ltc2389-16 conversion is controlled by cnvst . a falling edge on cnvst initiates the conversion process, which once begun, cannot be restarted until the con- version is complete. for optimum performance, cnvst should be driven by a clean, low jitter signal and transi- tions on data i/o lines should be avoided leading up to the falling edge of cnvst . converter status is indicated by the busy output, which remains high while the conversion is in progress. once cnvst is brought low to begin a conversion, it should be returned high either within 40ns from the start of the conversion or after the conversion is complete to ensure no errors occur in the digitized results. the cnvst timing required to take advantage of the reduced power nap mode of operation is described in the nap mode section. internal conversion clock the ltc2389-16 has an internal clock that is trimmed to achieve a maximum conversion time of 310 ns. no external adjustments are required and with a minimum acquisition time of 77 ns, a throughput performance of 2.5 msps is guaranteed in the parallel output modes. a pplications i n f ormation
ltc2389-16 30 238916f digital interface to accommodate a variety of application-specific proces- sor and fpga data bus widths, the ltc2389-16 output bus may be configured to operate in either 16- bit parallel, 8-bit parallel or serial modes, as described in table 1. the flexible ov dd supply allows the ltc2389-16 to commu- nicate with any digital logic operating between 1.8 v and 5v, including 2.5v and 3.3v systems. 16-bit parallel bus configuration in applications such as fpga and cpld based solutions or 16- bit microcontroller based solutions where a full 16-bit wide parallel data bus is available, the ltc2389-16 is capable of providing each conversion result r[15:0] as one 16- bit word on pins d[15:0]. to select this bus configuration, pin mode0 should be driven to mode0 = 0 and pin a1 should be driven to a1 = 0, as described in table 1. if the application does not require the bus to be shared, drive the chip select pin cs = 0 to enable the ltc2389-16 to drive the bus continuously, as shown in figure 14. in applications where the bus must be shared, drive cs = 1 when other devices are using the bus to hi-z the ltc2389-16 bus pins and drive cs = 0 to allow the ltc2389-16 to drive the bus , as shown in figures 15 and 16. 8-bit parallel bus configuration in applications such as 8- bit microcontroller based solu- tions where an 8- bit wide parallel data bus is available, the ltc2389-16 is capable of providing each conversion result r[15:0] in two 8- bit words on pins d[15:8]. to select this bus configuration, pin mode0 should be driven to mode0 = 0, as described in table 1. in this configuration, address input pin a1 controls whether the upper byte r[15:8] or the lower byte r[7:0] of the conversion result is driven on d[15:8], as shown in figure 17. note that, as shown in table 1, d[7:0] also functions as an 8- bit wide parallel bus with a1 providing control of the opposite polarity as it does on d[15:8]. use of d[7:0] as an 8- bit parallel bus should be avoided in applications where it is important to maintain compatibility with 18- bit versions of the ltc2389 family, as described in the pin compatibility with ltc2389-18 section. the chip select pin, cs, enables the 8- bit paral- lel bus to be shared between multiple devices. see the 16-bit parallel bus configuration section for further details. a pplications i n f ormation
ltc2389-16 31 238916f a pplications i n f ormation figure 14. read the parallel data continuously. the data bus is always driven and cannot be shared figure 15. read the parallel data after the conversion cs = 0, mode0 = 0, a1 = 0, mode1 = a0 = 0 t busylh t ddbusyl t conv cnvst busy data bus d[15:0] previous conversion current conversion 238916 f14 t cnvstl cs busy data bus d[15:0] mode0 = 0, a1 = 0, mode1 = a0 = 0 hi-z current conversion t en t dis 238916 f15 hi-z figure 16. read the parallel data during the following conversion data bus d[15:0] busy hi-z previous conversion t en t cnvstl t conv t busylh t dis 238916 f16 hi-z cnvst, cs mode0 = 0, a1 = 0, mode1 = a0 = 0 figure 17. 8-bit parallel interface using a1 pin cs a1 d[15:8] high 8 bits low 8 bits 8-bit interface hi-z hi-z 238916 f17 t en t dda1 t dis mode0 = 0, mode1 = a0 = 0
ltc2389-16 32 238916f a pplications i n f ormation figure 18. serial interface with external clock. read after the conversion. daisy chain multiple converters mode0 = 1, a1 = x, mode1 = a0 = 0 mode0 = 1, a1 = x, mode1 = a0 = 0 cs busy t en t ssdi sck starts low sck starts high t dsdo, t hsdo 1 2 3 d15 x15 x14 x13 x1 x0 238916 f18 d14 d13 d1 d0 x15 x14 4 15 16 17 18 sck sdo (adc 2) hi-z hi-z sdi (adc 2) t hsdi cs busy t en t ssdi t dsdo, t hsdo 1 2 3 d15 x15 x14 x13 x1 x0 d14 d13 d1 d0 x15 x14 4 15 16 17 18 sck sdo (adc 2) hi-z hi-z sdi (adc 2) t hsdi t sckh t sckl t sck t sckh t sckl t sck ltc2389-16 adc 1 adc 2 sdo cnvst in cs in sck in cnvst cs sck sdi ltc2389-16 sdo data out cnvst cs sck sdi t dsck t dsck
ltc2389-16 33 238916f a pplications i n f ormation serial bus configuration in applications where a serial bus is required to minimize the data bus width, the ltc2389-16 is capable of provid- ing each conversion result r[15:0] serially on pin d10/ sdo. to select this bus configuration, pin mode0 should be driven to mode 0 = 1, as described in table 1. address input pin a1 has no effect on the parsing or presentation of serial conversion data. as shown in figure 18, the serial output data is presented on the sdo pin in response to an external shift clock input applied to the sck pin. the data on sdo changes state following rising edges of sck. the one exception to this behavior is that d15 remains valid until the first sck rising edge following the first sck falling edge. if cs is used to gate the serial output data, the full conversion result should be read before cs is returned to a high level. for best performance, do not clock serial data out when busy is high. the sdi input pin can be used to daisy chain multiple converters, as shown in figure 18. in this figure, two devices are cascaded with the msb of adc1 appearing at the serial output of adc2 after a 16 sck cycle delay. the serial output of adc1 is clocked into adc2 on the falling edges of sck. this is useful in applications where hardware constraints limit the number of data lines available to interface with multiple converters. data format the binary format of the conversion result depends on the state of pins pd/ fd and ob/2c , as described in table?2. these pins are active in both the parallel and serial modes of operation. reset as shown in figure 19, when the reset pin is high, the ltc2389-16 is reset and the data bus is put into a high impedance mode. if this occurs during a conversion, the conversion is immediately halted. in reset, requests for new conversions are ignored. once reset returns low, the ltc2389-16 is ready to start a new conversion after the acquisition time has been met. figure 19. reset pin timing reset data bus d[15:0] hi-z cvnst t reseth t acq 238916 f19
ltc2389-16 34 238916f a pplications i n f ormation partial top silkscreen 238916 f20 board layout to obtain the best performance from the ltc2389-16, a printed circuit board ( pcb) is recommended. layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. pin compatibility with ltc2389-18 to ensure a board layout intended for use with the ltc2389-16 is also compatible with 18- bit versions of the ltc2389 family, the design should maintain the ability to drive pins 4 ( mode0) and 5 ( mode1) to both logic high and logic low levels, to dynamically drive pins 7 ( a0) and 8 (a1) to both logic high and logic low levels, and to read dynamic data driven by the ltc2389-18 on pins 7 ( a0) and 8 ( a1). additionally, if the 8- bit parallel bus configur- ation is used, the upper byte pins 28 through 21 (d[15:8]) of the output data bus should be used to read the conver- sion results. simplifications to these constraints are possible based on the specific application. for further details on the operation of the ltc2389-18, please refer to the associated data sheet. recommended layout the following is an example of a recommended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are shielded by ground. for more details and information refer to dc1826a-e, the evaluation kit for the ltc2389-16.
ltc2389-16 35 238916f a pplications i n f ormation partial layer 1 component side partial layer 2 ground plane 238916 f21 238916 f22
ltc2389-16 36 238916f a pplications i n f ormation partial layer 3 power plane partial layer 4 bottom layer bottom silk partial 238916 f23 238916 f24 238916 f25
ltc2389-16 37 238916f a pplications i n f ormation partial schematic of demo board vref pd/fdl csl ob/2cl ser_parl busy d15 d14 d13 d10/sdout d12 d7 d6 d5 d8 d3 d2 d1 d4 d0 ob/2cl ser_parl vref mode1 mode0 a1 a0 d9/sdin d11/sclk v+ vcmx2 vcmx2 +9v_in +3.3v +3.3v v+ vcmx2 v- v- vcmx2 r25 (opt) r25 (opt) jp2 ac dc -in jp2 ac dc -in 1 3 2 c6 0.1uf c6 0.1uf c12 10uf c12 10uf c7 1uf c7 1uf c30 10uf c30 10uf u1a ltc2389-16 mode0 4 mode1 5 ob/2cl 6 a0 7 a1 8 d0 9 d1 10 d2 11 d3 12 d4 13 d5 14 d6 15 d7 16 d8 21 d9/sdin 22 d10/sdout 23 d11/sclk 24 d12 25 d13 26 d14 27 d15 28 busy 29 pd/fdl 30 csl 31 reset 32 pd 33 cnvstl 34 refout 37 refin 38 refsense 39 -in 42 +in 43 vcm 36 r12 (opt) r12 (opt) r26 1k 0402 r26 1k 0402 c34 1uf c34 1uf u5 ltc6655bhms8-4.096 u5 ltc6655bhms8-4.096 shdn 1 vin 2 gnd 3 gnd 4 gnd 5 vout_s 6 vout_f 7 gnd 8 c10 10uf c10 10uf r10 (opt) 0402 r10 (opt) 0402 c19 1000pf 0805 c19 1000pf 0805 r16 10 r16 10 r20 0 ohm r20 0 ohm c32 (opt) c32 (opt) c22 10uf 6.3v c22 10uf 6.3v c29 1uf c29 1uf j3 ain- 0v - 4.096v j3 ain- 0v - 4.096v r7 (opt) 0402 r7 (opt) 0402 c33 (opt) c33 (opt) r30 402 1% r30 402 1% c21 1uf c21 1uf j2 ain+ 0v - 4.096v j2 ain+ 0v - 4.096v r34 300 0402 r34 300 0402 r31 (opt) r31 (opt) r38 300 0402 r38 300 0402 c16 (opt) c16 (opt) c18 (opt) c18 (opt) r24 1k 0402 r24 1k 0402 r41 0 ohm r41 0 ohm r28 10k 0402 r28 10k 0402 r11 (opt) r11 (opt) jp1 ac dc +in jp1 ac dc +in 1 3 2 r40 (opt) r40 (opt) on sw1 219-4mst cts electronic compo nents on sw1 219-4mst cts electronic compo nents 1 2 3 4 8 7 6 5 r36 10k 0402 r36 10k 0402 c17 ( opt) c17 ( opt) c20 0.1uf 0402 c20 0.1uf 0402 +in -in out u7a lt6201is8 +in -in out u7a lt6201is8 3 2 1 4 8 c9 1uf 0805 c9 1uf 0805 c14 (opt) 0805 c14 (opt) 0805 c24 (opt) c24 (opt) r42 (opt) r42 (opt) c8 (opt) 0805 c8 (opt) 0805 r21 49.9 0402 r21 49.9 0402 jp3 ext int cm jp3 ext int cm 1 3 2 r19 (opt) r19 (opt) c23 10uf c23 10uf r15 0 ohm r15 0 ohm c25 330pf c25 330pf r18 (opt) r18 (opt) c31 10uf c31 10uf e1 vref e1 vref c28 0.1uf 0402 c28 0.1uf 0402 r33 300 0402 r33 300 0402 r29 402 1% r29 402 1% r37 75 r37 75 e2 ext_cm e2 ext_cm r17 49.9 0402 r17 49.9 0402 r22 (opt) r22 (opt) r27 10 r27 10 r14 0 ohm r14 0 ohm r32 10k 0402 r32 10k 0402 c27 1uf c27 1uf c11 1000pf 0805 c11 1000pf 0805 c15 ( opt) c15 ( opt) r35 300 0402 r35 300 0402 r13 (opt) r13 (opt) out +in -in u7b lt6201is8 out +in -in u7b lt6201is8 5 6 7 c26 330pf c26 330pf r23 (opt) r23 (opt) r9 (opt) 0402 r9 (opt) 0402 r8 0 ohm 0402 r8 0 ohm 0402 r39 10k 0402 r39 10k 0402 c13 (opt) c13 (opt) tp2 busy tp2 busy +3.3v +3.3v +3.3v +3.3v +3.3v u2 nc7svu04p5x u2 nc7svu04p5x 4 2 5 3 c4 0.1uf c4 0.1uf r6 49.9 1% 1206 r6 49.9 1% 1206 j1 clk 100mhz max 3.3vpp j1 clk 100mhz max 3.3vpp c5 0.1uf c5 0.1uf r3 33 r3 33 r1 33 r1 33 c3 0.1uf c3 0.1uf r4 1k r4 1k r2 1k r2 1k tp1 cnvstl tp1 cnvstl u4 nc7svu04p5x u4 nc7svu04p5x 4 2 5 3 r5 33 0402 r5 33 0402 c1 0.1uf c1 0.1uf c2 0.1uf c2 0.1uf u3 nc7sz04p5x u3 nc7sz04p5x 4 2 5 3 u6 nl17sz74usg u6 nl17sz74usg d 2 cp 1 q 5 q 3 vcc 8 pr 7 gnd 4 clr 6 clk to cpld cnvst_33 from cpld +3.3v c35 0.1uf 0402 r43 0 ohm ovdd 18 vdd 19 vdd 3 vdd 47 vdd 46 vdd 45 vdd 40 vdd 2 gnd 17 gnd 1 gnd 20 gnd 35 gnd 41 gnd 44 gnd 48 +5v c42 0.1uf 0402 c41 10uf c40 0.1uf 0402 c40 0.1uf 0402 c39 0.1uf 0402 c39 0.1uf 0402 c43 0.1uf 0402 c43 0.1uf 0402 c36 10uf c36 10uf c38 0.1uf 0402 c38 0.1uf 0402 c37 0.1uf 0402 c37 0.1uf 0402 u1b ltc2389-16
ltc2389-16 38 238916f p ackage description lx package 48-lead plastic lqfp (7mm 7mm) (reference ltc dwg # 05-08-1760 rev ?) lx48 lqfp 0907 rev? 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 9.00 bsc a a 7.00 bsc 1 2 7.00 bsc 9.00 bsc 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note: 1. package dimensions conform to jedec #ms-026 package outline 2. dimensions are in millimeters 3. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 4. pin-1 indentifier is a molded indentation, 0.50mm diameter 5. drawing is not to scale see note: 4 c0.30 ? 0.50 r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 1 2 5.50 ref 7.15 ? 7.25 48 package outline recommended solder pad layout apply solder mask to areas that are not soldered section a ? a 0.50 bsc 0.20 ? 0.30 1.30 min please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc2389-16 39 238916f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage description uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc2389-16 40 238916f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0512 ? printed in usa r elate d p arts t ypical a pplication adc driver: single-ended input to differential output part number description comments adcs ltc2389-18 18-bit, 2.5msps, all-in-one adc 5v supply, pin-configurable input, 99.8db snr, 4.096v, 0v to 4.096v, and 2.048v input ranges, internal 4.096v reference, internal reference buffer, 7mm 7mm lqfp-48 and qfn-48 packages ltc2379-18/ltc2378-18/ ltc2377-18/ltc2376-18 18-bit,1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 101.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2369-18/ltc2368-18/ ltc2367-18/ltc2364-18 18-bit,1.6msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 96.5db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2370-16/ltc2368-16/ ltc2367-16/ltc2364-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2393-16/ltc2392-16/ ltc2391-16 16-bit, 1msps/500ksps/250ksps parallel/serial adc 5v supply, differential input, 94db snr, 4.096v input range, pin-compatible family in 7mm 7mm lqfp-48 and qfn-48 packages ltc2383-16/ltc2382-16/ ltc2381-16 16-bit, 1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 92db snr, 2.5v input range, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2756/ltc2757 18-bit, single serial/parallel i out softspan? dac 1lsb inl/dnl, ssop-28 / 7mm 7mm lqfp-48 package ltc2641 16-bit/14-bit/12-bit single serial v out dacs 1lsb inl/dnl, msop-8 package, 0v to 5v output ltc2751 16-bit/14-bit/12-bit single parallel i out softspan dac 1lsb inl/ dnl, software - selectable ranges, 5mm 7mm qfn-38 package references ltc6655 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift low noise buffered reference 5v/2.5v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt6200/lt6201 single/ dual 165mhz op amp with unity gain stability 0.95nv / hz (100 khz), low distortion: C 80db at 1 mhz, tsot23-6 package LT6230/lt6231/lt6232 single/ dual/ quad 215mhz rail- to- rail output low noise low power amplifiers 1.1nv/ hz (100khz), 3.5ma maximum, 350v maximum offset lt6202 /lt6203 single / dual 100mhz rail- to- rail input/ output low noise low power amplifiers 1.9nv hz (100khz), 3ma maximum, 100mhz gain bandwidth lt6350 low noise single-ended-to-differential adc driver rail-to-rail input and outputs, 240ns 0.01% settling time ltc1992 low power, fully differential input/output amplifier/ driver family 1ma supply current 238916 ta02 in ? in + 1nf 10 10 lowpass filters ltc2389-16 330pf 1nf 4.096v 0v 4.096v 0v 4.096v 0v + ? + ? 402 402 1/2 lt6201 v cm = 2.048v 1/2 lt6201 + ? 330pf 49.9 49.9

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